Title High-Performance and Time-Predictable Embedded Computing
Subtitle (River Publishers Series in Information Science and Technology)
Author Luis Miguel Pinho, Eduardo Quinones, Marko Bertogna, Andrea Marongiu, Vincent Nélis, Paolo Gai, Juan Sancho
ISBN 9788793609693
List price USD 106.00
Price outside India Available on Request
Original price
Binding Hardbound
No of pages 250
Book size 152 x 228 mm
Publishing year 2018
Original publisher River Publishers (Eurospan Group)
Published in India by .
Exclusive distributors Viva Books Private Limited
Sales territory India, Sri Lanka, Bangladesh, Pakistan, Nepal, .
Status New Arrival
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Nowadays, the prevalence of computing systems in our lives is so ubiquitous that we live in a cyber-physical world dominated by computer systems, from pacemakers to cars and airplanes. These systems demand for more computational performance to process large amounts of data from multiple data sources with guaranteed processing times. Actuating outside of the required timing bounds may cause the failure of the system, being vital for systems like planes, cars, business monitoring, e-trading, etc.

High-Performance and Time-Predictable Embedded Computing presents recent advances in software architecture and tools to support such complex systems, enabling the design of embedded computing devices which are able to deliver high-performance whilst guaranteeing the application required timing bounds.

  • Technical topics discussed in the book include:
  • Parallel embedded platforms
  • Programming models
  • Mapping and scheduling of parallel computations
  • Timing and schedulability analysis
  • Runtimes and operating systems

The work reflected in this book was done in the scope of the European project P SOCRATES, funded under the FP7 framework program of the European Commission. High-performance and time-predictable embedded computing is ideal for personnel in computer/communication/embedded industries as well as academic staff and master/research students in computer science, embedded systems, cyber-physical systems and internet-of-things.



List of Contributors

List of Figures

List of Tables

List of Abbreviations

Chapter 1: Introduction (Luis Miguel Pinho, Eduardo Quinones, Marko Bertogna, Andrea Marongiu,
Vincent Nélis, Paolo Gai and Juan Sancho
) • Introduction • The Convergence of High-performance and Embedded Computing Domains • Parallelization Challenge • The P-SOCRATES Project • Challenges Addressed in This Book • Compiler Analysis of Parallel Programs • Predictable Scheduling of Parallel Tasks on Many-core Systems • Methodology for Measurement-based Timing Analysis • Optimized OpenMP Tasking Runtime System • Real-time Operating Systems • The UpScale SDK • Summary • References

Chapter 2: Manycore Platforms (Andrea Marongiu, Vincent Nélis and Patrick Meumeu Yomsi) • Introduction • Manycore Architectures • Xeon Phi • Pezy SC • NVIDIA Tegra X1 • Tilera Tile • STMicroelectronics STHORM • Epiphany-V • TI Keystone II • Kalray MPPA-256 • The I/O subsystem • The Network-on-Chip (NoC) • The Host-to-IOS communication protocol • Internal architecture of the compute clusters • The shared memory • Summary • References

Chapter 3: Predictable Parallel Programming with OpenMP (Maria A. Serrano, Sara Royuela,
Andrea Marongiu and Eduardo Quinones
) • Introduction • Introduction to Parallel Programming Models • POSIX threads • OpenCLTM • NVIDIA® CUDA • Intel® CilkTM Plus • Intel® TBB • OpenMP • The OpenMP Parallel Programming Model • Introduction and Evolution of OpenMP • Parallel Model of OpenMP • Execution model • Acceleration model • Memory model • An OpenMP Example • Timing Properties of OpenMP Tasking Model • Sporadic DAG Scheduling Model of Parallel Applications • Understanding the OpenMP Tasking Model • OpenMP and Timing Predictability • Extracting the DAG of an OpenMP program • WCET analysis is applied to tasks and tasks parts • DAG-based scheduling must not violate the TSCs • Extracting the Timing Information of an OpenMP Program • Parallel Structure Stage • Parallel control flow analysis • Induction variables analysis • Reaching definitions and range analysis • Putting all together: The wave-front example • Task Expansion Stage • Control flow expansion and synchronization predicate resolution • tid: A unique task instance identifier • Missing information when deriving the DAG • Compiler Complexity • Summary • References

Chapter 4: Mapping, Scheduling, and Schedulability Analysis (Paolo Burgio, Marko Bertogna, Alessandra Melani, Eduardo Quinones and
Maria A. Serrano
) • Introduction • System Model • Partitioned Scheduler • The Optimality of EDF on Preemptive Uniprocessors • FP-scheduling Algorithms • Limited Preemption Scheduling • Limited Preemption Schedulability Analysis • Global Scheduler with Migration Support • Migration-based Scheduler • Putting All Together • Implementation of a Limited Preemption Scheduler • Overall Schedulability Analysis • Model Formalization • Critical Interference of cp-tasks • Response Time Analysis • Inter-task interference • Intra-task interference • Computation of cp-task parameters • Non-conditional DAG Tasks • Series–Parallel Conditional DAG Tasks • Schedulability Condition • Specializing Analysis for Limited Pre-emption Global/Dynamic Approach • Blocking Impact of the Largest NPRs (LP-max) • Blocking Impact of the Largest Parallel NPRs (LP-ILP) • LP worst-case workload of a task executing on c cores • Overall LP worst-case workload • Lower-priority interference • Computation of Response Time Factors of LP-ILP • Worst-case workload of ti executing on c cores: µi[c] • Overall LP worst-case workload of lp(k) per execution scenario s1: ?k[s1] • Complexity • Specializing Analysis for the Partitioned/Static Approach • ILP Formulation • Tied tasks • Untied tasks • Complexity • Heuristic Approaches • Tied tasks • Untied tasks • Integrating Interference from Additional RT Tasks • Critical Instant • Response-time Upper Bound • Scheduling for I/O Cores • Summary • References

Chapter 5: Timing Analysis Methodology (Vincent Nélis, Patrick Meumeu Yomsi and Luis Miguel Pinho) • Introduction • Static WCET Analysis Techniques • Measurement-based WCET Analysis Techniques • Hybrid WCET Techniques • Measurement-based Probabilistic Techniques • Our Choice of Methodology for WCET Estimation • Why Not Use Static Approaches? • Why Use Measurement-based Techniques? • Description of Our Timing Analysis Methodology • Intrinsic vs. Extrinsic Execution Times • The Concept of Safety Margins • Our Proposed Timing Methodology at a Glance • Overview of the Application Structure • Automatic Insertion and Removal of the Trace-points • How to insert the trace-points • How to remove the trace-points • Extract the Intrinsic Execution Time: The Isolation Mode • Extract the Extrinsic Execution Time: The Contention Mode • Extract the Execution Time in Real Situation: The Deployment Mode • Derive WCET Estimates • Summary • References

Chapter 6: OpenMP Runtime (Andrea Marongiu, Giuseppe Tagliavini and Eduardo Quinones) • Introduction • Offloading Library Design • Tasking Runtime • Task Dependency Management • Experimental Results • Offloading Library • Tasking Runtime • Applications with a linear generation pattern • Applications with a recursive generation pattern • Applications with mixed patterns • Impact of cutoff on LINEAR and RECURSIVE applications • Real applications • Evaluation of the Task Dependency Mechanism • Performance speedup and memory usage • The task dependency mechanism on the MPPA • Summary • References

Chapter 7: Embedded Operating Systems (Claudio Scordino, Errico Guidieri, Bruno Morelli, Andrea Marongiu, Giuseppe Tagliavini and Paolo Gai) • Introduction • State of The Art • Real-time Support in Linux • Hard real-time support • Latency reduction • Real-time CPU scheduling • Survey of Existing Embedded RTOSs • Classification of Embedded RTOSs • Requirements for The Choice of The Run Time System • Programming Model • Preemption Support • Migration Support • Scheduling Characteristics • Timing Analysis • RTOS Selection • Host Processor • Manycore Processor • Operating System Support • Linux • ERIKA Enterprise Support • Exokernel support • Single-ELF multicore ERIKA Enterprise • Support for limited preemption, job, and global scheduling • New ERIKA Enterprise primitives • New data structures • Dynamic task creation • IRQ handlers as tasks • File hierarchy • Early performance estimation • Summary • References


About the Editors

About the Editors:

Luis Miguel Pinho is Professor at the Department of Computer Engineering of the School of Engineering, Polytechnic Institute of Porto, Portugal, with a PhD in Electrical and Computer Engineering at the University of Porto, Portugal. He has more than 20 years of experience in research in the area of real-time and embedded systems, particularly in concurrent and parallel programming models, languages, and runtime systems. He is Research Associate in the CISTER research unit, where he was Vice-Director from 2010 to 2017, being responsible for creating several research areas and topics, among which the activities on parallel real-time systems, that he leads. He has participated in more than 20 R&D projects, was Project Coordinator and Technical Manager of the FP7 R&D European Project P-SOCRATES and national-funded CooperatES and Reflect Projects. He was also coordinator of the participation of CISTER and work package leader in several other international and national projects. He has published more than 100 papers in international conferences and journals in the area of real-time embedded systems. He was Senior Researcher of the ArtistDesign NoE and is currently a member of the HiPEAC NoE. He was Keynote Speaker at the 16th IEEE Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2010) and is the Editor-in-Chief of the Ada User Journal. Among others, he was General Co-Chair of the 28th GI/ITG International Conference on Architecture of Computing Systems (ARCS 2015), and Program Co-Chair of the 24th International Conference on Real-Time Networks and Systems (RTNS 2016) and of the 21st International Conference on Reliable Software Technologies (Ada-Europe 2016).

Eduardo Quinones is a senior researcher in the group on Interaction between the Computer Architecture and the Operating System (CAOS) at BSC and member of HIPEAC. He worked at the Intel Barcelona Research Center from 2002 till 2004 in compiler techniques for EPIC architectures (including Itanium I and II). At BSC, he has previous experiences involved in the architectural definition and the avionics case study definition in the MERASA FP7 project and he leads the architectural definition work packages of the PROARTIS and the parMERASA FP7 projects, and lead the applicability of HPC parallel programming models to real-time embedded systems to increase performance in the P-SOCRATES FP7 project. Moreover, he is involved in two research projects with the European Space Agency (ESA), one as a technical manager. His research area focuses on compiler techniques and many-core architectures for safety-critical systems on which he is coadvising six PhD students. He is currently the project coordinator for the CLASS H2020 project.

Marko Bertogna is Associate Professor at the University of Modena (Italy), where he leads the High-Perfomance Real-Time Systems Laboratory (HiPeRT Lab). His main research interests are in High-Performance Real-Time systems, especially based on multi- and many-core devices, Autonomous Driving and Industrial Automation systems, with particular relation to related timing and safety requirements. Previously, he was Assistant Professor at the Scuola Superiore Sant’Anna of Pisa, working at the Real-Time Systems Lab since 2003. He graduated magna cum laude in Telecommunication Engineering at the University of Bologna in 2002. From 2001 to 2002, he worked on integrated optical devices at the Technical University of Delft, The Netherlands. In 2006, he visited the University of North Carolina at Chapel Hill, working with prof. Sanjoy Baruah on scheduling algorithms for single and multicore real-time systems. In 2008, he received a PhD in Computer Sciences from the Scuola Superiore Sant’Anna of Pisa, with a dissertation on Real-Time Systems for Multicore Platforms, awarded as the best scientific PhD thesis discussed at Scuola Superiore Sant’Anna in 2008 and 2009.

Andrea Marongiu received the PhD degree in electronic engineering from the University of Bologna, Italy, in 2010. He has been a postdoctoral reserch fellow at ETH Zurich, Switzerland. He currently holds an assistant professor position at the University of Bologna (Department of Computer Science and Engineering). His research interests focus on programming models and architectures in the domain of heterogeneous multi- and many-core systems on a chip. This includes language, compiler, runtime and architecture support to efficiently address performance, predictability, energy and reliability issues in paralle, embedded systems, as well as HW-SW co-design of acceleratorbased MPSoCs. In this field, he has published more than 100 papers in international peer-reviewed conferences and journals, with more than 700 citations and an h-index of 16 [Google Scholar]. He has collaborated with several international research institutes and companies.

Vincent Nélis earned his PhD degree in Computer Science at the University of Brussels (ULB) in 2010. Since then, he has been working at CISTER as a Research Associate. He is an expert in real-time scheduling theory with a focus on multiprocessor/multicore systems and in interference analysis, including pre-emption cost analysis and bus/network contention analysis in multicores and many-cores systems. Vincent is regularly a member of technical program committees for international conferences, workshops, and journals. He has graduated 2 PhDs and he is currently the supervisor of a third PhD student. He has contributed to 5 R&D projects and published 25+ papers with about 30 different co-authors in international conferences and scientific journals. His work was awarded at several occasions: “Solvay Award” (2006), “Outstanding Paper Award” (2012), two “Best Paper Awards” (2010 and 2013) and a “Best Presentation Award” (2013).

Paolo Gai graduated (cum laude) in Computer Engineering at University of Pisa in 2000. He obtained the PhD from Scuola Superiore Sant’Anna in 2004. Since 2002 he is founder of Evidence Srl, a company providing innovations in the field of operating systems and platforms for embedded devices in the automotive and industrial fields.

His research activity is focused on the development of hard real-time architectures for embedded automotive control systems. His research interests include multi and many-core processor systems, object-oriented programming, real-time operating systems, scheduling algorithms, multimedia applications, and hypervisors.

Juan Sancho holds a degree in Telecommunications Engineering from the Universidad Politécnica de Valencia, Spain. He developed his Final Project Degree in the field of Health Monitoring using Wireless Sensor Networks at the Wireless Centre of the Copenhagen University of Engineering, Denmark. In the past he worked as network & systems engineer, participating in several European FP7, ENIAC and National projects (BUTLER, TOISE, SICRA, TSMART). Since 2014 he works as a Research & Innovation Engineer in ATOS Research & Innovation division, collaborating in FP7 and H2020 projects related to IoT topics (COSMOS, P-SOCRATES) and the Energy domain (inteGRIDy, ELVITEN, eDREAM). His research interests cover Big Data & Edge platforms, DevOps, Renewable Energy Sources, WSN and low-power embedded systems.

Target Audience:

People interested in Manycore platforms, high-performance embedded systems, parallel programming models, real-time systems, scheduling and schedulability, timing analysis, runtimes, operating systems.

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